Job ID: JR0168923
Job Category: Engineering
Primary Location: Hillsboro, OR US
Other Locations: US, Arizona, Phoenix;US, California, San Jose;US, California, Santa Clara
Job Type: Experienced Hire
System Validation EngineerJob Description
The mission of Intel’s Programmable Solutions Group (PSG) is to drive the future for FPGA and eASIC technology/solutions around the globe.
Within PSG, you'll be surrounded by some of the brightest minds/engineers in the world. Our System Validation Engineers are part of a vibrant cross-site team (US and Asia) who define validation strategies and develop the tests that we use to validate subsystem and platform integration for Intel's networking and server products across multiple roadmaps. We support a range of Network Data Accelerators and platform Hardware applications with our experienced Pre and Post-Si engineers.
An ideal candidate has general platform integration and debug expertise across a range of interfaces so they can pick up new technologies to architect, define, and develop test strategies and content that efficiently identifies issues at the RTL, FW, Integration or Specification level.
You will work with virtual platform simulation, FPGA emulation, and real hardware to ensure the devices meet our customers' specifications and use cases. Successful system validation engineers have a broad understanding of system architecture, RTL, firmware, and debug techniques, while routinely interfacing with Architecture, Design, Software and Pre-Silicon Validation teams.
Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
EducationBachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field (must have the required degree or expect the required degree by/before January 2022)
Minimum Qualifications6+ months of validation experience and/or an internship completed of which experience should include
- Scripting (e.g. PERL, TCL, Shell, Python)
- Experience working with test plans
- Experience working within a Linux/UNIX environment
Preferred QualificationsExperience in one or more of the following is a plus
- 5+ years of validation experience
- Experience developing test plans
- Experience in object-oriented programming
- Experience in software or Hardware System Bring-up or Silicon Power-On
- Developing test automation
- Developing and debugging Verilog
- Experience with system architecture preferably Intel Architecture/Arm Architecture
- Experience debugging or developing emulation models
- Experience designing and deriving testing for system clock/system reset flows
- PCIe protocol / PCIe interfaces testing experience
- Experience with lab equipment (Logic Analyzers, Oscilloscopes, protocol analyzers, JTAG/ITP debugger)
- Experience in Compression standards, Encryption standards, Virtualization standards
- Software Agile development process including DevOps
The Data Center Group (DCG) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.
US, Arizona, Phoenix;US, California, San Jose;US, California, Santa Clara
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.